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Customize your EAGLE software with community-created programs.
Make_bga ulp modified to create double letter names for large bgas. Skips extra letters s, x and z.
Hides all airwires except a group of airwires selected via the group command. Use \'RATS *\' at the command line to unhide all airwires. Modified version of Bob Starr\'s hide-airwires.ulp.
This ULP generates a script from an existing board that can be run in a library to create a device that represents the PCB with pogo pin holes that match the X/Y locations of SMD test points that contain the attribute \'POGOPIN\'. The SMD test points can be on the top or bottom side of the board and MUST also have an attribute of type \'POGOPIN\' defined for each test point that requires a hole location for mounting a pogo pin
Generates FPGA setup files from an Eagle board design. Currently generates VHDL port list from the pins of a specified part. Also generates the pin mapping for a Lattice Semiconductor .lpf file. Results must be edited for signaling types, but automatically generates a correct net name - pin mapping. May be extended for Verilog or Xilinx/Altera.
Latest version works with thru-hole and SMD test point pads. This ULP generates a script from an existing board that can be run in a library to create a device that represents the PCB with pogo pin holes that match the X/Y locations of SMD test points that contain the attribute \'POGOPIN\'. The SMD test points can be on the top or bottom side of the board and MUST also have an attribute of type \'POGOPIN\' defined for each test point that requires a hole location for mounting a pogo pin
v1.1 Update: Added smart mode option. Will only enable certain layers (tPlace, bStop, etc.) if the respective copper layer is already enabled. See description for more details and usage. Simple ULP to toggle layers. Intended to use with key shortcuts, but works fine in any application. Argument can be either layer name or number, or a mix of both. Only tested in Layout but should work in lib/lay/sch. No limit to number of arguments. Special CLI option to toggle all arguments the same direction or each individually.
Update of PSSCALE 3. Not compatible with Eagle 5\r\nUploaded by Soeren Theodorsen from Unknown
ULP to generate net definitions for AVR GCC projects from the schematic.
Check if the parts in the schematic are the same as in the corresponding libraries. Uses the Eagle\'s XML file format as data source. \r\nUploaded by Andrzej Telszewski from -
alignD.ulp is a rework of align.ulp with a dialog box for easy text entry and option comparisons. Sadly, like the original, it only works on parts in boards.