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Customize your EAGLE software with community-created programs.
Corrected Rank on auto generated Polygons.\r\nUploaded by A. Zaffran from CadSoft
This ULP creates the specific format surface mount XY location file, called a Centroid file, required by Screaming Circuits for prototype assembly. Simply run this ULP and include the generated file “ centroid.csv” in the zip file containing your BOM and Gerbers when you order prototype pcb assembly at www.ScreamingCircuits.com.\r\nUploaded by Duane Benson from Screaming Circuits, USA
Ersetzt Bohrdurchmesser in Bibliotheken durch Olimex-Standardgrößen.Erhöht anhand einer Liste in der ULP die Durchmesser normalerweise zusätzlich um 0,1mm, damit Durchkontaktierungsverluste ausgeglichen werden.Die Liste ist leicht editierbar.Ürsprüngliche Datei: round_drills_mm_all_.zip von Rindert NautaApril 2006 siegfriedschwemmer web de \r\nUploaded by Siegfried Schwemmer
Shows all parts in the board editor belonging to a specific sheet in the schematic. Functional circuit blocks can be organized in sheets which systematically group parts on the schematic level. \"show-from-sheet \" thus provides functional block highlighting on the board level. \"show-from-sheet group\" extends this functionality based on select.ulp to group all parts originating from a specified sheet.
Generates packages for SMT small outline ICs including SO, SOP, SSOP, TSOP, TSSOP and others.\r\nUploaded by Weartronics from http://www.weartronics.com/
Generates packages for SMT quad flat pack ICs including QFP, SQFP, TQFP, TSQFP and others.\r\nUploaded by Weartronics from http://www.weartronics.com/
This User Language Program asks the user to fill in their drawing information like paper size and perforation space description etc. and draws a drawing template with info box.\r\nUploaded by Richard Bekking from ROC Flevoland
This ULP can be used to automate filling out a frames docfield.Dieses ULP kann verwendet werden, um das Docfield eines Rahmens automatisiert auszufüllen.\r\nUploaded by René König
Generates a GenCad file (eg. used for Teradyne / GenRad In-Circuit-Testers) from the actual design. \r\nUploaded by Richard Hammerl from CadSoft
Latest export/replace project libraries modified from Eagle 6.4.0 version. Highly useful for cleaning up parts from bogus library part designers!!