Customize your EAGLE software with community-created programs.
This ULP simplifies the renaming of a net bringing the most commonly needed information together. Launched from a context menu for a net wire it provides easy access to: The first unused name in Eagle\'s default N$xx format The names of the nets already in use. The names of the visible pin names. connected to the net. Requires Eagle version 6.0.0 or later.
This ULP for v7.2 duplicates the placement of a hierarchical module given an x/y offset and source/destination module name instance. No routing duplication is supported, only the placement is duplicated. This is initial release of this ULP.
The latest version of BOM-EX for Eagle 7.2 with module support added.
Generates FPGA setup files from an Eagle board design. Currently generates VHDL port list from the pins of a specified part. Also generates the pin mapping for a Lattice Semiconductor .lpf file. Results must be edited for signaling types, but automatically generates a correct net name - pin mapping. May be extended for Verilog or Xilinx/Altera.
Autoplace ULP Creates grouping based on SCH and handles multiple sheets Based on V3-ULP by David Moodie, modified Version works with Eagle 6 and higher. By Lukas Obkircher
Shows all parts in the board editor belonging to a specific sheet in the schematic. Functional circuit blocks can be organized in sheets which systematically group parts on the schematic level. \"show-from-sheet \" thus provides functional block highlighting on the board level. \"show-from-sheet group\" extends this functionality based on select.ulp to group all parts originating from a specified sheet.
Context menu handler that turns off all airwires except the airwire selected.
Turn off all the airwires except the signal of interest from a context menu item. Show all airwires again by running the context item again using another wire type. The ULP will create the context menu required.
added options to renumber by a combination of X a Y directions in various percentages